How RTaW-Pegase will help you design of safe and optimized networks?
- Support your design choices by evidence — RTaW-Pegase computes performance metrics such as networks loads, communication delays and buffers utilization that make it possible to predict network performances in all use-cases. In addition, RTaW-Pegase offers features to investigate specific scenarios and compare the impact of different design and configuration options.
- Reduce time-to-market — our unique ZeroConfig-TSNⒸ (ZCT) generative design algorithm cut the development time of TSN networks by a factor 30 and more. Interested to see ZCT at work? Contact the product manager for a demo.
- Cost-optimize your networks — RTaW-Pegase enables you to avoid over-provisioning of resources (link speeds, memory in switches, unneeded technologies, etc). In addition, RTaW-Pegase includes design space exploration algorithms to optimize network topologies (e.g., number and location of switches), data streams routing and allocation of the software functions on the stations.
- Design for the future — you can know in advance the extent to which your networks will be able to support additional traffic thanks to our unique Topology Stress TestⒸ (TST) feature. Interested to discover how TST can help you? Contact the product manager for a demo.
- Results you can trust — RTaW-Pegase relies on Network Calculus that is accepted in aeronautics certification, its core algorithms are described in a formal manner in refereed scientific publications – see the technical papers co-authored with our partners.
- Proven in use — leading companies from the automotive, aerospace and industrial domains have been relying on RTaW-Pegase for their business since 2009 – see the companies that trust us.
Support industrial Ethernet, automotive switched Ethernet (incl. 802.1Q, AVB Credit-Based Shaper, TSN Time-Aware Shaper, frame preemption, 802.1CB, Some/Ip SD, DoIp, AVTP), time-triggered Ethernet (incl. SAE AS6802) as well as AFDX (ARINC664) with arbitrary speeds and topologies,
Support worst-case analysis and timing-accurate simulation of heterogeneous communication architectures made up of CAN (2.0A, 2.0B, CAN FD and ARINC825), switched Ethernet, AFDX, FlexRay, LIN and ARINC429 buses interconnected through gateways,
- New: Generative Design with ZeroConfig-TSN (ZCT)Ⓒ a “push-button” approach to automate the selection and configuration of TSN networks,
- New: Topology Stress Test (TST)Ⓒ design-space exploration algorithm helps designers make early-stage topological and technological choices without full knowledge of communication requirements,
- New: Higher-level communication layers, run-time environments and applications can be programmed as Java plug-ins. This allows the simulation of complete embedded systems,
- Optimized TSN Time-Aware Shaper (IEEE 802.11Qbv) transmission schedules for interconnected networks,
- Support Network-on-Chip for Kalray MPPA and STMicroelectronics manycore architectures,
- Analysis and configuration of task scheduling, Event-Triggered and Time-Triggered scheduling, independent tasks, tasks described as graphs and runnables, verification of system-wide timing chains across tasks, networks and CPUs,
- Implement the state of the art of Network Calculus to compute upper bounds on communication latencies, frame jitters and buffers utilization,
- Offer both worst-case analysis and timing-accurate simulation with a parallelized simulation engine to predict worst-case and typical performances,
- Support FIFO, priority, AVB credit-based shaper, TSN time-aware shaper, frame preemption, TTEthernet and round-robin frame schedulers,
- Include optimized priority allocation and routing algorithms, and configuration algorithms for AVB credit-based shaper and TSN time-aware shaper,
- Support periodic and sporadic message transmission patterns, UDP and TCP transmissions, segmented messages (e.g., video streams and FTP traffic), and complex transmission patterns (e.g., DoIp protocol),
- Rich graphical edition and visualization environment with communication architecture editor, Gantt diagrams, and comparison of design options,
- Easy import and export of network configurations and simulation results through Java export plug-ins, CSV, XML files and the common formats used in the industry,
- Maximum pessimism of the computed communication latencies with regard to the true worst-case latencies is limited (typically less than 15%) and is evaluated for each data stream,
- Include NETAIRBENCH, a benchmark generator to create random yet realistic Ethernet configurations for early stage evaluation or to study how the network will be able to accomodate more load in future evolutions,
- Extremely fast – for instance, large AFDX networks in civil airplanes are analysed in less than 10 seconds,
- Runs on all 32 or 64 bit platforms supporting Java – no dongle or license server protection,
- Professional support and custom extensions available. RTaW-Pegase functionalities are also available through software developers SDK for use in your own programs.
2020/02: Joint contribution with Volvo Cars on how to cost- and safety-optimize Ethernet-based communication architectures at the upcoming Automotive Ethernet Congress, 12-13 February 2020@Westin Grand Munich. We will be glad to meet with you at our booth.
2019/09: “Early-stage Topological and Technological Choices for TSN-based Communication Architectures” is a joint study with Renault Group presented at the 2019 IEEE Standards Association (IEEE-SA) Ethernet & IP @ Automotive Technology Day, Detroit, Mi, September 23-25, 2019. The presentation first introduces Renault Group’s FACE high-performance Service-Oriented-Architecture. RTaW’s Topology-Stress-Test approach is applied to quantify and maximize the number of Some/Ip services supported by the FACE E/E architecture. Download presentation slides here.
- 2019/04: CertiCAN is an academic tool produced using the Coq proof assistant for the formal certification of CAN analysis results developed at Verimag lab. in Grenoble, France. It has been used to prove the correctness of the results produced by the CAN analyzer of RTaW-Pegase – download the paper published at IEEE RTAS. A first time ever and it shows that proving result correctness is realistic in an industrial context.
- 2019/03: Topology Stress Test (TST)Ⓒ is a new design space exploration feature that enables designers to make early-stage topological and technological choices (speed, protocols, hardware) without full knowledge of communication requirements – Available with RTaW-Pegase v3.4.5.
- 2019/03: A hybrid approach for the verification of TSN networks combining the speed of machine learning and safety of worst-case analysis, presented at the 15th IEEE International Workshop on Factory Communication System (WFCS2019), Sundsvall, Sweden, May 27-29, 2019. Download the conference paper here.
- 2019/02: we had a booth at the Automotive Ethernet Congress in Munich, February 13-14, 2019. There were very good interactions among the 45 participants of our workshop entitled “Automating the Design of In-vehicle Ethernet Networks in 2020 and Beyond: the Beginning of the Centaur Era?” about how generative design, and AI at large, is going to re-shape the design of in-vehicle networks.
- 2019/01: Machine learning algorithms help drastically speed up the design space exploration of TSN networks. Download technical report here.
- 2018/10: we had a booth at the 2018 IEEE Standards Association (IEEE-SA) Ethernet & IP @ Automotive Technology Day, London, October 9-10, 2018. In the conference held along with the trade-show, we presented a study entitled “Insights into the performance and configuration of TCP in Automotive Ethernet Networks”. RTaW-Pegase now offers a complete support of TCP on top of TSN. Download presentation slides here.
- 2018/09: we had a booth at the TSN/A Conference 2018, Stuttgart, September 26-27, 2018. We showcased the latest features of RTaW-Pegase for automotive users (e.g., DoIp protocol support) and industrial users (e.g., design of bridging strategies in hierarchical networks).
- 2018/06: New Java plugin infrastructure to extend RTaW-Pegase with your own models to simulate the functional behaviors of ECUs or high-level protocols, as easy as it gets.
- 2018/04: “Pre-shaping bursty transmissions under IEEE802.1Q as a simple and efficient QoS mechanism” is a joint work with Renault Group and Onera presented at the WCX18: SAE World Congress Experience (WCX018), Detroit, USA, April 10-12, 2018. Extended version published in SAE International Journal of Passenger Cars—Electronic and Electrical Systems, 11(3):2018. Download paper – Download presentation slides.
- 2018/02: “Insights on the performance and configuration of AVB and TSN in automotive networks” is a joint work with Renault Group presented at the 9th Embedded Real-Time Software and Systems Congress (ERTS 2018), Toulouse, France, January 31 – February 2, 2018. Download white paper here.
- 2018/02: “Computing Routes and Delay Bounds for the Network-on-Chip of the Kalray MPPA-256 Bostan Processor” is a joint study with Kalray and Onera presented at the 9th Embedded Real-Time Software and Systems Congress (ERTS 2018), Toulouse, France, January 31 – February 2, 2018. Download paper here.
- 2018/01: we had a booth at the Automotive Ethernet Congress in Munich, January 30-31, 2018 where we showcased for the first time ZeroConfig-TSNⒸ and presented a joint work with Renault Group entitled: “Performance Assessment of Configuration Strategies for Automotive Ethernet”.
- 2017/10: “Experimental assessment of QoS protocols for in-car Ethernet networks” is a joint study with Renault Group and Onera presented at the 2017 IEEE Standards Association (IEEE-SA) Ethernet & IP @ Automotive Technology Day, San-Jose, October 31-November 2, 2017. Download presentation slides here.
- 2017/09: “Insights on the performance and configuration of AVB and TSN in automotive applications” is a joint study with Renault Group and Onera presented at the TSN/A Conference 2017, Stuttgart, September 20-21, 2017.
- 2017/02: We had a booth at the Automotive Ethernet Congress in Munich, February 7–8, 2017. We demoed use-cases of RTaW-Pegase on heterogeneous in-car communication architectures (CAN, CAN-FD and Ethernet) built on Autosar compliant communication stacks.
- 2017/01: Support Network-on-Chip for Kalray MPPA (worst-case analysis) and STMicroelectronics (simulation) manycore architectures,
- 2016/09: We had a booth at the IEEE-SA Ethernet & IP @ Automotive Technology Day (E&IP@ATD). This event about the evolution of Ethernet standards, technologies and applications in the automotive domain took place at the Mariott Rive Gauche in Paris on September 20-21, 2016.
- 2016/08: Underlying Network Calculus, the main timing analysis technique in RTaW-Pegase, is the (min,+) algebra. For people interested in the theory of Network-Calculus, we are glad to make the (min,+) Algebra Playground freely available on-line.
- 2015/11: TTEthernet (SAE AS6802) and time-triggered communication (eg. using IEEE1588) supported in RTaW-Pegase. This technical paper presented at ERTS2016 studies the interactions between the different classes of traffic in TTEthernet.
- 2015/08: RTaW and ONERA (the French Aerospace Lab) sign a scientific partnership in the field of timing verification for Ethernet networks. We are thrilled to strengthen our 5+ years collaboration with ONERA.
- 2015/04: “Timing verification of automotive Ethernet networks: what can we expect from simulation?“, study co-authored with Daimler Cars presented at the SAE World Congress, Detroit, USA, April 21-23, 2015. Slides are available here. See also the follow-up paper presented at ERTS2016.
- 2015/03: Automotive Ethernet study led by Daimler Cars using the Some/IP model of RTaW-Pegase: “Formal Analysis of the Startup Delay of SOME/IP Service Discovery“, presented at DATE 2015, Grenoble, France, March 9-13, 2015.
- 2015/02: RTaW had a booth at the Automotive Ethernet Congress in Munich, February 4–5, 2015, and showcased the new timing-accurate simulation engine.
- 2014/02: RTaW had a booth at the ERTSS congress in Toulouse, February 5–7, 2014. Two papers closely related to RTaW-Pegase were presented at the conference that takes place along with the trade-show – please see below,
- 2013/12: Modeling the frame scheduling on the sending end enables to compute much more precise bounds on the communication latencies with RTaW-Pegase, study co-authored with Onera and Thales Avionics presented at ERTSS2014,
- 2013/12: Proof-by-Instance for Embedded Network Design: From Prototype to Tool Roadmap, study co-authored with Onera and Inria presented at ERTSS 2014 on how to prove the correctness of frame worst-case response time calculations,
- 2013/08: Latest release includes NETAIRBENCH, a benchmark generator to create random but realistic switched Ethernet and AFDX configurations according to a set of user-defined parameters,
- 2013/07: Certifying the correctness of Network Calculus computations done in RTaW-Pegase, publication at EUCASS 2013 and second study published at ITP’2013,
- 2013/06: On the use of Deficit Round-Robin to facilitate incremental certification and mixed criticality scheduling, study presented at EUCASS 2013 co-authored with Onera and Thales Avionics,
- 2012/02: Comprehensive experimental study of RTaW-Pegase on hundreds of realistic AFDX configurations co-authored with Onera and Thales Avionics at ERTSS 2012,
- 2011/11: RTaW-Pegase received the best demo award at the Open Demo Session of Real-Time Techniques and Technologies of the 32nd IEEE Real-Time Systems Symposium,
- 2011/10: paper proving the correctness of some key algorithms implemented in RTaW-Pegase presented at the 1st International Workshop on Worst-case Traversal Time (download paper),
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