How RTaW-Pegase will help you design of safe and optimized Ethernet and AFDX networks?
- Support your design choices by evidence — RTaW-Pegase computes performance metrics such as link loads, communication latencies and buffers utilization that make it possible to predict network performances in all possible use-cases. In addition, RTaW-Pegase offers features to investigate specific scenarios and compare the impact of different design and configuration alternatives.
- Cost-optimize your networks — RTaW-Pegase provides bounds on the communication latencies that are provably close to the actual worst-case situation, avoiding thus the over-provisioning of resources. In addition, RTaW-Pegase includes design space exploration algorithms to optimize network topologies (e.g., number and location of switches), data streams routing and allocation of the software functions on the stations.
- Design for the future — using RTaW-Pegase, you know in advance the extent to which your networks will be able to grow in future evolutions of a system.
- Results you can trust — RTaW-Pegase is no black-box software you have to blindly trust the results of. RTaW-Pegase relies on Network Calculus that is accepted in aeronautics certification, its core algorithms are described in a formal manner in refereed scientific publications – see the technical papers co-authored with our partners.
- Benefits from years of know-how and experience in mission-critical systems — RTaW-Pegase, which builds on more than 15 years of timing verification research, has been developed in partnership with Onera (see announcement here) and it has been chosen by leading companies from the aerospace and industrial domains – see the companies that trust us.
- Ready for certification: whatever your application domain and safety standards, we can deliver what you need in certification projects.
- Best value for money — RTaW-Pegase is not only the most accurate timing analysis tool on the market, it is also less expensive than competitors’ solutions and we provide company-wide license – but don’t take our word for it, request a free evaluation version.
- Your investment is secured — in order to protect your mission-critical technology, we can contract with you a source code escrow agreement.
- Support industrial Ethernet, automotive switched Ethernet (incl. 802.1Q, AVB credit-based shaper, TSN time-aware shaper, frame preemption, Some/Ip SD), time-triggered Ethernet (incl. SAE AS6802) as well as AFDX (ARINC664) with arbitrary speeds and topologies,
- Support worst-case analysis and simulation of heterogeneous communication architectures made up of CAN (2.0A, 2.0B, CAN FD and ARINC825), switched Ethernet, AFDX and ARINC429 buses interconnected through gateways,
- Support Network-on-Chip for Kalray MPPA and STMicroelectronics manycore architectures,
- New: analysis and configuration of task scheduling, Event-Triggered and Time-Triggered scheduling, independent tasks, tasks described as graphs and runnables, verification of system-wide timing chains across tasks, networks and CPUs.
- Implement the state of the art of Network Calculus to compute upper bounds on communication latencies, frame jitters and buffers utilization,
- Offer both worst-case analysis and timing-accurate simulation with a parallelized simulation engine to predict worst-case and typical performances,
- Support FIFO, priority, AVB credit-based shaper, TSN time-aware shaper, frame preemption, TTEthernet and round-robin frame schedulers,
- Include optimized priority allocation and routing algorithms, and configuration algorithms for AVB credit-based shaper and TSN time-aware shaper,
- Support periodic and sporadic message transmission patterns, as well as segmented messages (e.g., video streams)
- Rich graphical edition and visualization environment with communication architecture editor, Gantt diagrams, and comparison of design options,
- New: Higher-level communication layers, run-time environments and applications can be programmed in the CPAL language. This allows the simulation of complete embedded systems,
- Easy import and export of network configurations and simulation results through CSV, XML files and the common formats used in the industry,
- Maximum pessimism of the computed communication latencies with regard to the true worst-case latencies is limited (typically less than 15%) and is evaluated for each data stream,
- Include NETAIRBENCH, a benchmark generator to create random yet realistic Ethernet/AFDX configurations for early stage evaluation or to study how the network will be able to accomodate more load in future evolutions,
- Extremely fast – for instance, large AFDX networks in civil airplanes are analysed in less than 10 seconds,
- Runs on all 32 or 64 bit platforms supporting Java – no dongle or license server protection,
- Professional support and custom extensions available. RTaW-Pegase functionalities are also available through software developers SDK for use in your own programs.
News and upcoming events
- 2017/10: “Experimental assessment of QoS protocols for in-car Ethernet networks” is a joint study with Renault Group and Onera that presented at the upcoming 2017 IEEE Standards Association (IEEE-SA) Ethernet & IP @ Automotive Technology Day, San-Jose, October 31-November 2, 2017. Slides can be downloaded here.
- 2017/09: “Insights on the performance and configuration of AVB and TSN in automotive applications” is a joint study with Renault Group and Onera presented at the TSN/A Conference 2017, Stuttgart, September 20-21, 2017.
- 2017/02: We had a booth at the Automotive Ethernet Congress in Munich, February 7–8, 2017. We demoed use-cases of RTaW-Pegase on heterogeneous in-car communication architectures (CAN, CAN-FD and Ethernet) built on Autosar compliant communication stacks.
- 2017/01: Support Network-on-Chip for Kalray MPPA (worst-case analysis) and STMicroelectronics (simulation) manycore architectures,
- 2016/09: We had a booth at the IEEE-SA Ethernet & IP @ Automotive Technology Day (E&IP@ATD). This event about the evolution of Ethernet standards, technologies and applications in the automotive domain took place at the Mariott Rive Gauche in Paris on September 20-21, 2016.
- 2016/08: Underlying Network Calculus, the main timing analysis technique in RTaW-Pegase, is the (min,+) algebra. For people interested in the theory of Network-Calculus, we are glad to make the (min,+) Algebra Playground freely available on-line.
- 2015/11: TTEthernet (SAE AS6802) and time-triggered communication (eg. using IEEE1588) supported in RTaW-Pegase. This technical paper to be presented at ERTS2016 studies the interactions between the different classes of traffic in TTEthernet.
- 2015/08: RTaW and ONERA (the French Aerospace Lab) sign a scientific partnership in the field of timing verification for Ethernet networks. We are thrilled to strengthen our 5+ years collaboration with ONERA.
- 2015/04: “Timing verification of automotive Ethernet networks: what can we expect from simulation?“, study co-authored with Daimler Cars presented at the SAE World Congress, Detroit, USA, April 21-23, 2015. Slides are available here. See also the follow-up paper to be presented at ERTS2016.
- 2015/03: Automotive Ethernet study led by Daimler Cars using the Some/IP model of RTaW-Pegase: “Formal Analysis of the Startup Delay of SOME/IP Service Discovery“, presented at DATE 2015, Grenoble, France, March 9-13, 2015.
- 2015/02: RTaW had a booth at the Automotive Ethernet Congress in Munich, February 4–5, 2015, and showcased the new timing-accurate simulation engine.
- 2014/02: RTaW had a booth at the ERTSS congress in Toulouse, February 5–7, 2014. Two papers closely related to RTaW-Pegase were presented at the conference that takes place along with the trade-show – please see below,
- 2013/12: Modeling the frame scheduling on the sending end enables to compute much more precise bounds on the communication latencies with RTaW-Pegase, study co-authored with Onera and Thales Avionics presented at ERTSS2014,
- 2013/12: Proof-by-Instance for Embedded Network Design: From Prototype to Tool Roadmap, study co-authored with Onera and Inria presented at ERTSS 2014 on how to prove the correctness of frame worst-case response time calculations,
- 2013/08: Latest release includes NETAIRBENCH, a benchmark generator to create random but realistic switched Ethernet and AFDX configurations according to a set of user-defined parameters,
- 2013/07: Certifying the correctness of Network Calculus computations done in RTaW-Pegase, publication at EUCASS 2013 and second study published at ITP’2013,
- 2013/06: On the use of Deficit Round-Robin to facilitate incremental certification and mixed criticality scheduling, study presented at EUCASS 2013 co-authored with Onera and Thales Avionics,
- 2012/02: Comprehensive experimental study of RTaW-Pegase on hundreds of realistic AFDX configurations co-authored with Onera and Thales Avionics at ERTSS 2012,
- 2011/11: RTaW-Pegase received the best demo award at the Open Demo Session of Real-Time Techniques and Technologies of the 32nd IEEE Real-Time Systems Symposium,
- 2011/10: paper proving the correctness of algorithms implemented in RTaW-Pegase presented at the 1st International Workshop on Worst-case Traversal Time (download paper),
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