Challenges of Next-Generation Electronic Architectures in the SDV Era

Software has become the key to innovation and is transforming entire industries. If Software-Defined Vehicles (SDV) open up a wealth of possibilities in terms of innovation, customization and differentiation, they also pose intricate challenges to E/E architectures:

Demand for more safety-critical and compute-intensive functions such as ADAS and ultimately autonomous driving,
High-performance and timing-predictable networking solutions to cope with the dramatic increase in bandwidth demand created by increasing number of bandwidth-demanding sensors such as cameras,
Consolidation of today’s numerous “domain ECU’s” into a small number of high-performance multi-domain integration platforms with redundancy requirements,
Over-the-Air (OTA) updates and vehicle-to-cloud real-time communication,
Safety- and performance- scalable E/E architectures to meet the needs of the different vehicle classes in a cost-effective manner – see this study by R. Bosch and Cognifyer, RTaW’s research lab,
Predictability of highly-complex execution platforms comprising one or several different OSes, possibly a hypervisor, a service-oriented middleware, running on SoCs with heterogeneous cores – see this study by Volvo Cars and Cognifyer.

Speed-up Design Exploration, Optimization and Validation of Next-Generation SDVs with RTaW-Pegase/SDV Platform

System Level Modelling, Configuration and Design-Space Exploration

Unified Modeling and Simulation for Networks and Software in a Single Platform

DDS- and SOME/IP-based Service Oriented Architectures

RTaW and RTI have partnered to provide DDS & TSN solutions for mission-critical systems.

Compare design options - here, effect on loads & latencies of periodic activations vs event-triggered activations

Further information in this case-study

Key Features

Allow to model the software running on the processors as tasks communicating through messages and signals, locally or over a communication network,
Support design choices in terms of tasks allocation to processors and cores, scheduling policy and task activation patterns,
Model system-level timing chains, e.g. between sensors and actuators, over the processors and networks making up the embedded system,
Provide firm guarantees that processors’ loads are on budget and tasks’ timing constraints are met,
Timing-accurate simulation and worst-case response time analysis for software functions, network transmissions and sensor-to-actuator timing chains,
Allow to dimension buffer sizes so that no message is lost,
Support Service Oriented Architectures (SOME/IP, DDS) and validate that services are delivered on time, every time,
Provide rich visualisation features (e.g., Gantt charts, loads) to understand the system’s timing behaviour at run time, both in nominal and in corner cases,
Quantify system extensibility in terms of spare processor loads, number of additional functions and services that the architecture can support,
Explore SDV design candidates and make performance and cost-driven design choices,
Support industry standard file formats (e.g., Autosar .arxml) to fit into the overall design flow,
Integrate seamlessly with Pegase network modules for system-level evaluation (e.g. for distributed control).